EUV Lithography as the Binding Constraint on AI Scaling
The machine
An EUV lithography tool costs $300-400 million and is the most complex machine humanity produces at volume. Four major subsystems, each with supply chains spanning 10,000+ entities:
- EUV light source — fires a laser at tin droplets three times in sequence to generate 13.5nm light
- Reticle stage — positions the mask pattern
- Wafer stage — positions the silicon wafer with sub-nanometer overlay accuracy across layers
- Carl Zeiss optics — the only supplier of the mirror systems
The math
Per gigawatt of AI compute (using Nvidia Rubin on 3nm):
- ~55,000 wafers of 3nm logic
- ~6,000 wafers of 5nm
- ~170,000 wafers of HBM memory
- Each 3nm wafer needs ~20 EUV passes
- Total: ~2 million EUV wafer passes per GW
- At 75 wafers/hour, 90% uptime: 3.5 EUV tools per GW
ASML production trajectory:
- 2025: ~70 tools/year
- 2026: ~80 tools/year
- 2030: ~100 tools/year
- Cumulative installed base by 2030: ~700 tools
If all 700 tools were allocated to AI (they won’t be — phones, automotive, and other chips also need EUV): ~200GW ceiling.
Sam Altman’s stated target of 52GW/year by 2030 would claim roughly 25% of total EUV capacity.
Why this bottleneck is different
Power is solvable with money and engineering (behind-the-meter generation, batteries, gas turbines from 16+ manufacturers). Memory capacity is solvable with new fab construction (2-year lag). EUV is solvable only by ASML scaling production of machines that take years to build and test, using supply chains that haven’t yet internalized the scale AI requires.
Dylan Patel: “Everyone’s doing X minus one. In some cases, they’re doing X divided by two, because they’re not AGI-pilled.”
Connection to CUDA moat
CUDA Programmability Moat - Why Flexibility Beats Optimization explains why Nvidia captures value at the chip design layer. This note explains why the chip manufacturing layer constrains how much total compute exists. Both are durable advantages — CUDA because it’s an ecosystem, EUV because it’s a physical bottleneck with a single supplier.
Related Notes
- CUDA Programmability Moat - Why Flexibility Beats Optimization — the design-layer moat that sits on top of the manufacturing constraint
- AI and Investing Thesis — parent hub
- Inference Cost Collapse and Frontier Model Margin Expansion — falling inference costs operate within the EUV-constrained compute ceiling
- Two Exponentials - AI Capability vs Economic Diffusion — EUV constrains the capability exponential’s slope
- AI Memory Crowding - HBM Eats Consumer Device Budgets — two binding constraints on AI scaling: logic (EUV) and memory (HBM)
- AI Stack Value Accrual - Chip, Infra, Intelligence, App — EUV is the binding constraint on the chip layer of the value accrual stack
- Dylan Patel / SemiAnalysis — source